?2004 by catalyst semiconductor, inc. characteristics subject to change without notice. doc. no. 1089, rev. l h a l o g e n f r e e tm l e a d f r e e cs sk di do v cc nc org gnd 1 2 3 4 8 7 6 5 cs sk di do v cc org gnd 1 2 3 4 8 7 6 5 v cc cs sk org gnd do di 1 2 3 4 8 7 6 5 cs sk di do v cc org gnd 1 2 3 4 8 7 6 5 nc nc nc 1 2 3 4 8 7 6 5 v cc nc org gnd cs sk di do 8 7 6 5 v cc org gnd di cs sk do 1 2 3 4 nc cat93c66 (die rev. e) 4k-bit microwire serial eeprom features high speed operation: 1mhz low power cmos technology 1.8 to 6.0 volt operation selectable x8 or x16 memory organization self-timed write cycle with auto-clear hardware and software write protection power-up inadvertant write protection 1,000,000 program/erase cycles 100 year data retention commercial, industrial and automotive temperature ranges sequential read green package option available pin configuration dip package (p, l) soic package (j,w) catalyst? advanced cmos eeprom floating gate tech- nology. the devices are designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. the devices are available in 8-pin dip, 8-pin soic, 8-pin tssop and 8-pad tdfn packages. description the cat93c66 is a 4k-bit serial eeprom memory device which isconfigured as either registers of 16 bits (org pin at v cc ) or 8 bits (org pin at gnd). each register can be written (or read) serially by using the di (or do) pin. the cat93c66 is manufactured using soic package (s,v) soic package (k,x) tssop package (u,y) tdfn package (rd4, zd4) bottom view functional symbol note: when the org pin is connected to vcc, the x16 organiza- tion is selected. when it is connected to ground, the x8 pin is selected. if the org pin is left unconnected, then an internal pullup device will select the x16 organization. cs sk nc org do di v cc gnd pin functions pin name function cs chip select sk clock input di serial data input do serial data output v cc +1.8 to 6.0v power supply gnd ground org memory organization nc no connection
2 cat93c66 doc. no. 1089, rev. l d.c. operating characteristics v cc = +1.8v to +6.0v, unless otherwise specified. symbol parameter test conditions min typ max units i cc1 power supply current f sk = 1mhz 3 ma (write) v cc = 5.0v i cc2 power supply current f sk = 1mhz 500 a (read) v cc = 5.0v i sb1 power supply current cs = 0v 10 a (standby) (x8 mode) org=gnd i sb2 power supply current cs=0v 0 10 a (standby) (x16mode) org=float or v cc i li input leakage current v in = 0v to v cc 1 a i lo output leakage current v out = 0v to v cc ,1 a (including org pin) cs = 0v v il1 input low voltage 4.5v v cc < 5.5v -0.1 0.8 v v ih1 input high voltage 4.5v v cc < 5.5v 2 v cc + 1 v v il2 input low voltage 1.8v v cc < 4.5v 0 v cc x 0.2 v v ih2 input high voltage 1.8v v cc < 4.5v v cc x 0.7 v cc +1 v v ol1 output low voltage 4.5v v cc < 5.5v 0.4 v i ol = 2.1ma v oh1 output high voltage 4.5v v cc < 5.5v 2.4 v i oh = -400 a v ol2 output low voltage 1.8v v cc < 4.5v 0.2 v i ol = 1ma v oh2 output high voltage 1.8v v cc < 4.5v v cc - 0.2 v i oh = -100 a absolute maximum ratings* temperature under bias .................. -55 c to +125 c storage temperature ........................ -65 c to +150 c voltage on any pin with respect to ground (1) ............. -2.0v to +v cc +2.0v v cc with respect to ground ................ -2.0v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. reliability characteristics symbol parameter reference test method min typ max units n end (3) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (3) data retention mil-std-883, test method 1008 100 years v zap (3) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (3)(4) latch-up jedec standard 17 100 ma note: (1) the minimum dc input voltage is 0.5v. during transitions, inputs may undershoot to 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from 1v to v cc +1v.
3 cat93c66 doc. no. 1089, rev. l pin capacitance symbol test conditions min typ max units c out (1) output capacitance (do) v out =0v 5 pf c in (1) input capacitance (cs, sk, di, org) v in =0v 5 pf instruction set n o i t c u r t s n it i b t r a t se d o c p o s s e r d d aa t a d s t n e m m o c 8 x6 1 x8 x6 1 x d a e r10 10 a - 8 a0 a - 7 a0 a n a s s e r d d a d a e r e s a r e11 10 a - 8 a0 a - 7 a0 a n a s s e r d d a r a e l c e t i r w11 00 a - 8 a0 a - 7 a0 d - 7 d0 d - 5 1 d0 a n a s s e r d d a e t i r w n e w e10 0 x x x x x 1 1x xx x x x 1 1x x e l b a n e e t i r w s d w e10 0 x x x x x 0 0x xx x x x 0 0x x e l b a s i d e t i r w l a r e10 0 x x x x x 0 1x xx x x x 0 1x x s e s s e r d d a l l a r a e l c l a r w10 0 x x x x x 1 0x xx x x x 1 0x x 0 d - 7 d0 d - 5 1 ds e s s e r d d a l l a e t i r w limits v cc = v cc = v cc = 1.8v-6v 2.5v-6v 4.5v-5.5v test symbol parameter conditions min max min max min max units t css cs setup time 200 100 50 ns t csh cs hold time 0 0 0 ns t dis di setup time 400 200 100 ns t dih di hold time 400 200 100 ns t pd1 output delay to 1 1 0.5 0.25 s t pd0 output delay to 0 1 0.5 0.25 s t hz (1) output delay to high-z 400 200 100 ns t ew program/erase pulse width 10 10 10 ms t csmin minimum cs low time 1 0.5 0.25 s t skhi minimum sk high time 1 0.5 0.25 s t sklow minimum sk low time 1 0.5 0.25 s t sv output delay to status valid 1 0.5 0.25 s sk max maximum clock frequency dc 250 dc 500 dc 1000 khz a.c. characteristics c l = 100pf (3)
4 cat93c66 doc. no. 1089, rev. l a.c. test conditions input rise and fall times 50ns input pulse voltages 0.4v to 2.4v 4.5v v cc 5.5v timing reference voltages 0.8v, 2.0v 4.5v v cc 5.5v input pulse voltages 0.2v cc to 0.7v cc 1.8v v cc 4.5v timing reference voltages 0.5v cc 1.8v v cc 4.5v power-up timing (1)(2) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. (3) the input levels and timing reference points are shown in ac test conditions table. device operation the cat93c66 is a 4096-bit nonvolatile memory in- tended for use with industry standard microprocessors. the cat93c66 can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 11-bit instructions control the reading, writing and erase opera- tions of the device. when organized as x8, seven 12-bit instructions control the reading, writing and erase opera- tions of the device. the cat93c66 operates on a single power supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indi- cates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy 1 into the di pin. the do pin will enter the high impedance state on the falling edge of the clock (sk). placing the do pin into the high impedance state is recommended in applications where the di pin and the do pin are to be tied together to form a common di/o pin. the format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 8-bit address (an additional bit when organized x8) and for write operations a 16-bit data field (8-bit for x8 organizations). read upon receiving a read command and an address (clocked into the di pin), the do pin of the cat93c66 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). for the cat93c66, after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential read mode. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit. all subsequent data words will follow without a dummy zero bit. write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear and data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c66 can be determined by selecting the device and polling the do pin. since this device features auto- clear before write, it is not necessary to erase a memory location before it is written into.
5 cat93c66 doc. no. 1089, rev. l figure 1. sychronous data timing figure 2. read instruction timing sk di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data valid t sklow sk cs di do high-z 11 0 a n a n 1 a 0 dummy 0 d 15 . . . d 0 or d 7 . . . d 0 1 11 1 111 11111111 address + 1 d 15 . . . d 0 or d 7 . . . d 0 address + 2 d 15 . . . d 0 or d 7 . . . d 0 address + n d 15 . . . or d 7 . . . don't care figure 3. write instruction timing sk cs di do t csmin standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew
6 cat93c66 doc. no. 1089, rev. l erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c66 can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical 1 state. erase/write enable and disable the cat93c66 powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat93c66 write and clear instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. erase all upon receiving an eral command, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c66 can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical 1 state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93c66 can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. figure 4. erase instruction timing sk cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0
7 cat93c66 doc. no. 1089, rev. l figure 7. wral instruction timing figure 5. ewen/ewds instruction timing figure 6. eral instruction timing sk cs di standby 10 0 * * enable=11 disable=00 sk cs di do standby t cs high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 status verify sk cs di do standby high-z 10 1 busy ready t sv t hz t ew t csmin d n d 0 0 0
8 cat93c66 doc. no. 1089, rev. l ordering information notes: (1) the device used in the above example is a 93c66si-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating volta ge, tape & reel) (2) product die revision letter is marked on top of the package as a suffix to the production date code (e.g., ayww e .) for additional information, please contact your catalyst sales office. package p = pdip s = soic (jedec) j = soic (jedec) k = soic (eiaj) u = tssop rd4 = tdfn (3x3mm) zd4 = tdfn (3x3mm, lead free, halogen free) l = pdip (lead free, halogen free) v = soic, jedec (lead free, halogen free) w = soic, jedec (lead free, halogen free) x = soic, eiaj (lead free, halogen free) y = tssop (lead free, halogen free) prefix device # suffix 93c66 s i te13 product number tape & reel -1.8 cat temperature range blank = commercial (0 c - 70 c) i = industrial (-40 c - 85 c) a = automotive (-40 c - 105 c) operating voltage blank (v cc =2.5 to 6.0v) 1.8 (v cc =1.8 to 6.0v) optional company id e = extended (-40 c to + 125 c) die revision 93c66: e rev e (2)
copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 1089 revison: l issue date: 5/14/04 revision history e t a dn o i s i v e rs t n e m m o c 4 0 / 4 1 / 5 0l s t r a p . 6 8 / 6 6 / 7 5 / 6 5 / 6 4 c 3 9 t a c m o r f d e t a e r c t e e h s a t a d w e n d n a 6 7 c 3 9 t a c , 6 6 c 3 9 t a c , 7 5 c 3 9 t a c , 6 5 c 3 9 t a c , 6 5 c 3 9 t a c s t e e h s a t a d e l g n i s o t n i d e t a t r a p e s n e e b e v a h 6 8 c 3 9 t a c r e t t e l d i n o i s i v e r e i d d d a s e r u t a e f e t a d p u n o i t p i r c s e d e t a d p u n o i t i d n o c n i p e t a d p u m a r g a i d l a n o i t c n u f d d a n o i t c n u f n i p e t a d p u s c i t s i r e t c a r a h c g n i t a r e p o . c . d e t a d p u e c n a t i c a p a c n i p e t a d p u t e s n o i t c u r t s n i e t a d p u n o i t a r e p o e c i v e d e t a d p u n o i t a m r o f n i g n i r e d r o e t a d p u y r o t s i h n o i s i v e r e t a d p u r e b m u n v e r e t a d p u
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